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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs advanced* white electronic designs corp. reserves the right to change products or speci cations without notice. june 2006 rev. 0 wv3eg6437s-d4 256mb ? 2x16mx64 ddr sdram so-dimm, unbuffered description the wv3eg6437s is a 2x16mx64 double data rate sdram memory module based on 256mb ddr sdram components. the module consists of eight 16mx16 ddr sdrams in 66 pin tsop package mounted on a 200 pin fr4 substrate. * this product is under development, is not quali ed or characterized and is subject to change without notice. features unbuffered double-data-rate architecture ddr300 and ddr400 ? jedec design speci cations bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2.5, 3 programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh, (8k/64ms refresh) serial presence detect with eeprom dual rank power supply: v cc = v cc : 2.5v 0.2v (ddr300) v cc = v ccq : 2.6v 0.1v (ddr400) jedec standard 200 pin so-dimm package ? package height options: d4: 31.75mm (1.25") typ note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option operating frequencies ddr400@cl=3 ddr333@cl=2.5 clock speed 200mhz 166mhz cl-t rcd -t rp 3-3-3 2.5-3-3
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 pin names a0 ? a12 address input ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs7 data strobe input/output ck0, ck1 clock inputs ck0#, ck1# cke0, cke1 clock enable inputs cs0#, cs1# chip select inputs ras# row address strobe cas# column address strobe we# write enable dm0-dm7 data mask v cc power supply v ss ground v ref reference power supply v ccspd serial eeprom power supply sda serial data i/o scl spd clock input sa0-sa2 spd address nc no connect pin configurations pin symbol pin symbol pin symbol pin symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7 dq1 57 v cc 107 a5 157 v cc 8 dq5 58 v cc 108 a4 158 ck1# 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 ck1 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 nc 121 cs0# 171 dq50 22 v cc 72 nc 122 cs1# 172 dq54 23 dq9 73 nc 123 nc 173 v ss 24 dq13 74 nc 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 nc 127 dq32 177 dq56 28 v ss 78 nc 128 dq36 178 dq60 29 dq10 79 nc 129 dq33 179 v cc 30 dq14 80 nc 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 nc 133 dqs4 183 dqs7 34 v cc 84 nc 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 nc
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 functional block diagram cs1# cs0# dqs0 dm0 dqs1 dm1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs2 dm2 dqs3 dm3 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# dqs4 dm4 dqs5 dm5 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqs6 dm6 dqs7 dm7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# ldqs ldm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 cs# a0 sa0 serial pd sda a1 sa1 a2 sa2 ba0, ba1 a0-a12 ras# ba0, ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams we#: ddr sdrams cas# cke0 we# v ref v ss ddr sdrams ddr sdrams cke1: ddr sdrams cke1 wp scl v ccspd v cc ddr sdrams ddr sdrams ddr sdrams ddr sdrams clock wiring clock input ck0/ck0# ck1/ck1# 4 sdrams 4 sdrams spd ddr sdrams ck0/1 ck0/1# r=120 note: all resistor values are 22 ohms 5% unless otherwise speci ed.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -0.5 to 3.6 v storage temperature t stg -55 to +150 c operating temperature t a 0 - 70 c power dissipation p d 8w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc characteristics 0c t a 70c parameter symbol min max unit supply voltage ddr333 v cc 2.3 2.7 v i/o supply voltage ddr333 v ccq 2.3 2.7 v supply voltage ddr400 v cc 2.5 2.7 v i/o supply voltage ddr400 v ccq 2.5 2.7 v i/o reference voltage v ref 0.49 + v cc 0.51 + v cc v i/o termination voltage v tt v ref - 0.04 v ref + 0.04 v input logic high voltage v ih(dc) v ref + 0.15 v cc + 0.30 v input logic low voltage v il(dc) -0.3 v ref - 0.15 v input voltage level, ck and ck# v in(dc) -0.3 v cc + 0.30 v input differential voltage, ck and ck# v id(dc) 0.36 v cc + 0.60 v input crossing point voltage, ck and ck# v ix(dc) 0.3 v cc + 0.60 v input leakage current addr, cas#, ras#, we# i i -16 16 a cs#, cke -8 8 a ck, ck# -8 8 a dm -4 4 a output leackage current dq, dqs i oz -10 10 a output high surrent (normal strength) v out = v tt + 0.84v i oh -16.8 - ma output high surrent (normal strength) v out = v tt - 0.84v i ol 16.8 - ma output high surrent (half strength) v out = v tt + 0.45v i oh -9 - ma output high surrent (half strength) v out = v tt - 0.45v i ol 9-ma notes: 1. v ref is expected to equal 0.5*v ccq of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/-2 percent of the dc value. 2. v tt in sot applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. v id is the magnitude of the difference between the input level on ck and the input level of ck#. 4. v ccq of all ic's are ited to v cc .
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 ac operating conditions all voltages referenced to v ss parameter symbol min. max. units notes input high (logic1) voltage v ih(ac) v ref + 0.31 v 1 input low (logic0) voltage v il(ac) v ref - 0.31 v 1 input differential voltage, ck and ck# input v id(ac) 0.7 v ccq + 0.6 v input crossing point voltage, ck and ck# input v ix(ac) 0.5*v cc - 0.2 0.5*v cc + 0.2 v notes: 1. v ih overshoot: v in = v cc + 1.5v for a pulse width 3ns and the pulse can not be greater than 1/3 of the cycle rate. v il undershoot: v il = -1.5v for a pulse width 3ns and the pulse can not be greater than 1/3 of the cycle rate. input/output capacitance t a = 25c, f = 100mhz parameter symbol min max units input capacitance (a0~a12, ba0~ba1, ras#, cas#, we#) c in1 20 28 pf input capacitance (cke0, cke1) c in2 12 16 pf input capacitance (cs0#, cs1#) c in3 12 16 pf input capacitance ck, ck0#, ck1, ck1#) c in4 12 16 pf input capacitance (dm0 ~ dm7), (dqs0 ~ dqs7) c in5 12 14 pf input capacitance (dq0 ~ dq63) c out1 12 14 pf
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 i cc specifications and test conditions parameter symbol conditions ddr403 @cl=3 max ddr333 @cl=2.5 max units operating current i cc0* one device bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 456 372 ma operating current i cc1* one device bank; active-read-precharge; burst = 2; t rc =t rc (min);t ck =t ck (min) ; iout = 0ma; address and control inputs changing once per clock cycle. 616 512 ma precharge power- down standby current i cc2p** all device banks idle; power- down mode; t ck =t ck (min); cke=(low) 32 24 ma idle standby current i cc2f** cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. vin = vref for dq, dqs and dm. 240 240 ma active power-down standby current i cc3p** one device bank active; power-down mode; t ck (min); cke=(low) 400 280 ma active standby current i cc3n** cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 520 440 ma operating current i cc4r* burst = 2; reads; continous burst; one device bank active;address and control inputs changing once per clock cycle; t ck =t ck (min); iout = 0ma. 736 652 ma operating current i cc4w** burst = 2; writes; continous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing twice per clock cycle. 736 652 ma auto refresh current i cc5** t rc =t rc (min) 1,600 1,440 ma self refresh current i cc6** cke 0.2v 24 24 ma operating current i cc7* four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 1,416 1,332 ma note: i cc speci cation is based on samsung components. other dram manufacturers speci cation may be different. * value calculated as one module rank in this operation condition, and all other module ranks in i cc2p (cke low) mode. ** value calculated re ects all module ranks in the operating condition.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 ddr sdram component electrical characteristics and recommended ac operating conditions ac characteristics 403 335 units parameter symbol min max min max access window of dqs from ck/ck# t ac -0.65 +0.65 -0.7 +0.7 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 t ck clock cycle time cl = 3 t ck (3) 510 ns cl = 2.5 t ck (2.5) 612ns dq and dm input hold time relative to dqs t dh 0.40 0.40 ns dq and dm input setup time relative to dqs t ds 0.40 0.40 ns dq and dm input pulse width (for each input) t dipw 1.75 1.75 ns access window of dqs from ck/ck# t dqsck -0.55 +0.65 -0.60 +0.60 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.40 0.45 ns write command to rst dqs latching transition t dqss 0.72 1.28 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.20 0.20 t ck dqs falling edge from ck rising - hold time t dsh 0.20 0.20 t ck half clock period t hp t ch(min) or t cl(min) t ch(min) or (min) ns data-out high-impedance window from ck/ck# t hz +0.65 +0.70 ns data-out low-impedance window from ck/ck# t lz -0.65 -0.70 ns address and control input hold time (1 v/ns) t ihf 0.60 0.75 ns address and control input setup time (1 v/ns) t isf 0.60 0.75 ns address and control input hold time (0.5 v/ns) t ihs 0.70 0.80 ns address and control input setup time (0.5 v/ns) t iss 0.70 0.75 ns address and control input pulse width (for each input) t ipw 2.20 2.20 ns load mode register command cycle time t mrd 10 10 ns dq-dqs hold, dqs to rst dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns data hold skew factor t qhs 0.50 0.55 ns active to precharge command t ras 40 70k 42 70k ns active to read with auto precharge command t rap 15 18 ns active to active/auto refresh command period t rc 55 60 ns auto refresh command period t rfc 70 72 ns active to read or write delay t rcd 15 18 ns precharge command period t rp 15 18 ns dqs read preamble t rpre 0.90 1.10 0.9 1.10 t ck dqs read postamble t rpst 0.40 0.60 0.4 0.60 t ck active bank a to active bank b command t rrd 10 12 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 00ns note: ac speci cation is based on samsung components. other dram manufactures speci cation may be different. continued on next page
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 ddr sdram component electrical characteristics and recommended ac operating conditions (continued) ac characteristics 403 355 parameter symbol min max min max units dqs write postamble t wpst 0.40 0.60 0.40 0.60 t ck write recovery time t wr 15 15 ns internal write to read command delay t wtr 21t ck average periodic refresh interval t refi 7.80 7.80 s exit self refresh to non-read command t xsnr 75 75 ns exit self refresh to read command t xsrd 200 200 t ck auto precharge write recovery + precharge time t ral t wr /t ck + t rp /t ck t wr /t ck + t rp /t ck t ck note: ac speci cation is based on samsung components. other dram manufactures speci cation may be different.
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 * all dimensions are in millimeters and (inches) package dimensions for d4 3.81 (0.150) max 1.10 (0.043) 0.90 (0.035) pin 1 67.75 (2.667) 67.45 (2.656) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ (2x) pin 199 pin 200 pin 2 front view 2.15 (0.085) 6.00 (0.240) 2.504 (63.60) 2.55 (0.100) 1.00 (0.039) typ typ back view 31.90 (1.256) 31.60 (1.244) 47.40 (1.866) typ 11.40 (0.449) typ 4.2 (0.165) typ 3.90(0.154) 4.10(0.161) 4.06 (0.160) 1.80 (0.071) 1.50 (0.059) ordering information for d4 part number speed/data rate frequency height* wv3eg6437s403d4xxg 200mhz/400mbps, cl=3 31.75 (1.25") typ wv3eg6437s335d4xxg 166mhz/333mbps, cl=2.5 31.75 (1.25") typ notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci c part numbers are used to provide memory components source control. the place holder for this is shown as lower case ?x? in t he part numbers above and is to be replaced with the respective vendors code. consult factory for quali ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 part numbering guide wv 3 e g 64 37 s xxx d4 x x g wedc memory ddr gold bus width 2x16m 2.5v speed (mb/s) package 200 pin industrial temp option (for commercial leave "blank" for industrial add "i" component vendor name (m = micron) (s = samsung) (n = nanya) g = rohs compliant
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs june 2006 rev. 0 white electronic designs corp. reserves the right to change products or speci cations without notice. advanced wv3eg6437s-d4 document title 256mb ? 32mx64, ddr sdram unbuffered dram die options: ? samsung: h-die (k4h561638h-ucb3) rohs ? micron: t26a: f-die revision history rev # history release date status rev 0 created june 2006 advanced

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